In numerous computing applications, systems designed to allow multiple precesses to concurrently access the data stored in a shared memory outperform systems allowing only exclusive memory access. As an example, consider the cooperation of a computer and video display. As data stored in shared memory is created by the computer for display, the video display controller is repetitively accessing the shared memory for refreshing the display screen. When the shared memory includes multiport memory, random access by the computer and serial access by the display controller cooperate independently. Independent access eliminates the possibility of delaying the computing process or slowing the display process throughput due to conflicting needs for exclusive access.
System throughput for an asynchronous system design may exceed throughput of an equivalent synchronous system design, however, the synchronous system approach is generally less expensive to design, manufacture, and maintain. In a synchronous system design, the operations of logic circuits, processors, and memory coincide with a continuous, i.e. free running, system clock signal. Operations are begun after an active edge of the system clock signal and results are made available for further processing before the active edge of a subsequent period of the system clock signal. The system clock signal is simultaneously received by all data storage elements (flip-flops, registers, counters, etc.) to synchronize, i.e. to clock, the operations of individual elements of the system. Since signals subject to accumulated propagation delays through series logic elements are resynchronized between steps of a complex operation, the design need not be concerned with matching propagation path lengths, manufacturing can accommodate wider tolerances in individual device timing characteristics, and testing is simplified.
It is desirable to apply the benefits of synchronous design to applications for multiport memory. In conventional multiport memory such as video random access memory (VRAM), the serial port includes a serial clock signal, a bidirectional data signal line, and a serial output enable signal. When reading the serial port, a sequentially selected bit from a selected row of bits is provided on the data signal line for each serial clock signal received when the serial output is enabled. However, it is the system designer's responsibility to discontinue provision of the clock signal to discontinue serial read access. When writing the serial port, data on the bidirectional data signal line must be held substantially after the active edge of the serial clock. Synchronous systems providing the data signal are generally unable to hold a signal after the active edge of the system clock used as the serial clock signal. The conventional VRAM is, therefore, unsuited to synchronous design.
External circuitry for synchronizing the operation of a conventional VRAM serial port reduces throughput. An external gate in series with the serial clock signal is necessary to discontinue provision of a free running clock signal. By introducing an external gate in series with the system clock, the designer must accommodate the maximum propagation delay through the gate. Accommodating additional delay decreases throughput.
As an example of another computing application where it is desirable to use multiport memory in synchronous design, consider communications network nodes. Communications networks are conventionally serial to limit the number of connections, or channels, between communicating stations. At the conventional node, the communications data rate is considerably faster than the computing speed of the necessary logic or microprocessor circuits used to recognize the messages communicated. In such an application improved communications reliability is made possible by synchronizing the operation of the logic or microprocessor and the communications link. When the data rate greatly exceeds the computing speed, several conventional multiport memories must be combined in FIFO buffer and interleaved buffer designs. As a consequence of obtaining sufficient serial data rate capability, design costs increase due to complexity of the design involving several memories. Manufacturing costs increase due to increased connections, tighter timing margins, and complex tests. In addition, the cost of achieving high reliability increases dramatically.
In view of the problems described above and related problems that consequently become apparent to those skilled in the applicable arts, the need remains in numerous computing applications for a multiport memory operable from a free running system clock signal. Such applications include, for example, those involving video display, serial communication, and data storage.